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issi is27lv020 integrated silicon solution, inc. 1 ep019-0a 12/19/97 issi reserves the right to make changes to its products at any time without notice in order to improve design and supply the be st possible product. we assume no responsibility for any errors which may appear in this publication. ? copyright 1997, integrated silicon solution, inc. features ? single 2.7v to 3.6v power supply ? fast access time: 90 ns ? jedec-approved pinout ? low power consumption 20 m a (max) cmos standby current 10 ma (max) active current at 5 mhz ? high-speed programming typically less than 16 seconds ? industrial and commercial temperature ranges available ? standard 32-pin dip, plcc and tsop packages description the issi is27lv020 is a low voltage, low power, high-speed 1 megabit (256k-word by 8-bit) cmos programmable read- only memory. it utilizes the standard jedec pinout making it funtionally compatible with the is27c020 eprom. the is27lv020 operates from a 2.7v to 3.6v power supply. the superior access time combined with low power consump- tion is the result of innovative design and process technology. maximum power consumption in standby mode is 72 m w. if the device is constantly accessed at 5 mhz, then the maximum power consumption is increased to 36 mw. these power ratings are significantly lower than the standard is27c020 eprom. the is27lv020 uses issi ' s write programming algorithm which allows the entire chip to be programmed in typically less than 30 seconds. this product is available in one-time programmble (otp) pdip, plcc, and tsop packages over commercial and industrial temperature ranges. is27lv020 262,144 x 8 low voltage cmos eprom issi functional block diagram vcc gnd oe output enable chip enable and prog logic 2,097,152-bit cell matrix ce pgm output buffers y gating x decoder y decoder 18 a0-a17 8 dq0-dq7 advance information december 1997
issi is27lv020 2 integrated silicon solution, inc. ep019-0a 12/19/97 pin configurations 32-pin dip pin descriptions a0-a17 address inputs ce ( e ) chip enable input dq0-dq7 data inputs/outputs oe ( g ) output enable input pgm ( p ) program enable input vcc power supply voltage v pp program supply voltage gnd ground nc no internal connection 32-pin plcc 32-pin tsop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 vpp a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 gnd vcc pgm (p) a17 a14 a13 a8 a9 a11 oe (g) a10 ce (e) dq7 dq6 dq5 dq4 dq3 dq1 dq2 gnd dq3 dq4 dq5 dq6 a12 a15 a16 vpp vcc pgm (p) a17 a14 a13 a8 a9 a11 oe (g) a10 ce (e) dq7 a7 a6 a5 a4 a3 a2 a1 a0 dq0 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 index 4 3 2 1 32 31 30 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a11 a9 a8 a13 a14 a17 pgm (p) vcc vpp a16 a15 a12 a7 a6 a5 a4 oe (g) a10 ce (e) dq7 dq6 dq5 dq4 dq3 gnd dq2 dq1 dq0 a0 a1 a2 a3
issi is27lv020 integrated silicon solution, inc. 3 ep019-0a 12/19/97 functional description programming the is27lv020 upon delivery, the is27lv020 has 2,097,152 bits in the "one", or high state. "zeros" are loaded into the is27lv020 through the procedure of programming. the programming mode is entered when 12.5v 0.25v is applied to the v pp pin, v cc = 6v, ce and pgm is at v il , and oe is at v ih . for programming, the data to be programmed is applied eight bits in parallel to the data output pins. the write programming algorithm reduces programming time by using 100 m s programming pulses followed by a byte verification to determine whether the byte has been successfully programmed. if the data does not verify, an additional pulse is applied for a maximum of 25 pulses. this process is repeated while sequencing through each address of the eprom. the write programming algorithm programs and verifies at v cc = 6v and v pp = 12.5v. after the final address is completed, all byte are compared to the original data with v cc = 5.25v. program inhibit programming of multiple is27lv020s in parallel with dif- ferent data is also easily accomplished. except for ce , all like inputs of the parallel is27lv020 may be common. a ttl low-level program pulse applied to an is27lv020 ce input with v pp = 12.5v 0.25v, pgm low and oe high will program that is27lv020. a high-level ce input inhibits the other is27lv020 from being programmed. program verify a verify should be performed on the programmed bits to determine that they were correctly programmed. the verify should be performed with oe and ce at v il , pgm at v ih , and v pp between 12.25v and 12.75v. auto select mode the auto select mode allows the reading out of a binary code from an eprom that will identify its manufacturer and type. this mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding program- ming algorithm. this mode is functional in the 25 c 5 c ambient temperature range that is required when pro- gramming the is27lv020. to activate this mode, the programming equipment must force 12.0v 0.5v on address line a9 of the is27lv020. two identifier bytes may then be sequenced from the device outputs by toggling address line a0 from v il to v ih . all other address lines must be held at v il during auto select mode. byte 0 (a0 = v il ) represents the manufacturer code, and byte 1 (a0 = v ih ), the device identifier code. for the is27lv020, these two identifier bytes are given in the mode select table. all identifiers manufacturer and device codes will possess odd parity, with the msb (dq7) defined as the parity bit. read mode the is27lv020 has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. chip enable ( ce ) is the power control and should be used for device selection. assuming that addresses are stable, address access time (t acc ) is equal to the delay from ce to output (t ce ). output enable ( oe ) is the output control and should be used to get data to the output pins, independent of device selection. data is available at the outputs t oe after the falling edge of oe assuming that ce has been low and addresses have been stable for at least t acc C t oe . standby mode the is27lv020 has a standby mode which reduces the maximum v cc active current. it is placed in standby mode when ce is at v cc 0.3v. the amount of current drawn in standby mode depends on the frequency and the number of address pins switching. the is27lv020 is specified with 50% of the address lines toggling at 5 mhz. a reduction of the frequency or quantity of address lines toggling will significantly reduce the actual standby cur- rent.
issi is27lv020 4 integrated silicon solution, inc. ep019-0a 12/19/97 truth table (1,2) mode ce ce ce ce ce oe oe oe oe oe pgm pgm pgm pgm pgm a0 a9 v pp outputs read v il v il xxxv cc d out output disable v il v ih xxxv cc hi-z standby v ih xxxxv cc hi-z program v il v ih v il xxv pp d in program verify v il v il v ih xxv pp d out program inhibit v ih xxxxv pp hi-z auto select (3,5) manufacturer code v il v il xv il v h v cc d5h device code v il v il xv ih v h v cc 0eh notes: 1. v h = 12.0v 0.5v. 2. x = either v ih or v il . 3. a1-a8 = a10-a17 = v il . 4. see dc programming characteristics for v pp voltage during programming. 5. the is27lv020 can use the same write algorithm during program as other is27c020 or is27020 devices. logic symbol output or-tieing to accommodate multiple memory connections, a two- line control function is provided to allow for: 1. low memory power dissipation, and 2. assurance that output bus contention will not occur. it is recommended that ce be decoded and used as the primary device-selecting function, while oe be made a common connection to all devices in the array and con- nected to the read line from the system control bus. this assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particular memory device. system applications during the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of chip enable. the magnitude of these transient current peaks is dependent on the output capaci- tance loading of the device at a minimum, a 0.1 m f ceramic capacitor (high-frequency, low inherent inductance) should be used on each device between v cc and gnd to mini- mize transient effects. in addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on eprom arrays, a 4.7 m f bulk electrolytic capacitor should be used between v cc and gnd for each eight devices. the location of the capacitor should be close to where the power supply is connected to the array. 18 8 dq0-dq7 a0-a17 ce (e) pgm (p) oe (g)
issi is27lv020 integrated silicon solution, inc. 5 ep019-0a 12/19/97 absolute maximum ratings (1) symbol parameter value unit v term terminal voltage with respect to gnd all pins except a9 and v pp C0.6 to v cc + 0.5 (2) v v pp v cc C 0.3 to 13.5 (2,3) v a9 C0.6 to 13.5 (2,3) v v cc C0.6 to 7.0 (2) v t a ambient temperature with power applied C65 to +125 c t stg storage temperature (otp) C65 to +125 c t stg storage temperature (all others) C65 to +150 c notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. minimum dc input voltage is C0.5v. during transitions, inputs may undershoot to C2.0v for periods less than 10 ns. maximum dc voltage on output pins is vcc + 0.5v which may overshoot to vcc + 2.0v for periods less than 10 ns. 3. maximum dc voltage on a9 or v pp may overshoot to +13.5v for periods less than 10 ns. operating range range ambient temperature v cc commercial 0 c to +70 c 2.7 C 3.6v industrial (1) C40 c to +85 c 2.7 C 3.6v note: 1. operating ranges define those limits between which the functionally of the device is guaranteed. dc electrical characteristics (1,2,3) (over operating range) symbol parameter test conditions min. max. unit v oh output high voltage v cc = min., i oh = C400 m a 2.4 v v ol output low voltage v cc = min., i ol = 2.0 ma 0.4 v v ih input high voltage (4) 2.0 v cc + 0.5 v v il input low voltage (4) C0.3 0.8 v i li input load current v in = 0v to +v cc 5 m a i lo output leakage current v out = 0v to +v cc 5 m a notes: 1. v cc must be applied simultaneously or before v pp and removed simultaneously or after v pp . never try to force v pp low to 1v below v cc . manufacturer suggests to tie v pp and v cc together during the read operation. 2. caution: the is27lv020 must not be removed from (or inserted into) a socket when v cc or v pp is applied. 3. minimum dc input voltage is C0.5v. during transitions, the inputs may undershoot to C2.0v for periods less than 10 ns. maximum dc voltage on output pins is v cc + 0.5v which may overshoot to v cc + 2.0v for periods less than 10 ns. 4. tested under static dc conditions.
issi is27lv020 6 integrated silicon solution, inc. ep019-0a 12/19/97 power supply characteristics (1,2,5) (over operating range) symbol parameter test conditions min. max. unit i cc 1 vcc operating v cc = max., ce = v il 10ma supply current (3) i out = 0 ma, f = 5 mhz (open outputs) i pp 1 v pp current during v cc = max., ce = oe = v il 10 m a read (4) v pp = v cc i ccsb 0 vcc cmos standby ce = v cc + 0.3v (no toggling) 20 m a current i ccsb 1 vcc ttl standby ce = v ih (no toggling) 200 m a current notes: 1. v cc must be applied simultaneously or before v pp and removed simultaneously or after v pp . never try to force v pp low to 1v below v cc . manufacturer suggests to tie v pp and v cc together during the read operation. 2. caution: the is27lv020 must not be removed from (or inserted into) a socket when v cc or v pp is applied. 3. i cc 1 is tested with oe = v ih to simulate open outputs. 4. maximum active power usage is the sum of i cc and i pp . 5. minimum dc input voltage is C0.5v. during transitions, the inputs may undershoot to C2.0v for periods less than 10 ns. maximum dc voltage on output pins is v cc + 0.5v which may overshoot to v cc + 2.0v for periods less than 10 ns. capacitance (1,2,3) symbol parameter conditions typ. max. unit c in input capacitance v in = 0v 8 10 pf c out output capacitance v out = 0v 8 12 pf notes: 1. typical values are for nominal supply voltage. 2. this parameter is only sampled, but not 100% tested. 3. test conditions: t a = 25 c, f = 1 mhz. switching test circuit 1.2k w device under test 3.3v 6.0k w c l 100 pf switching test waveform 2.4v 0.4v 2.0v 0.8v 2.0v 0.8v input output notes: ac testing: 1. inputs are driven at 2.4v for a logic "1" and 0.4v for a logic "0". 2. input pulse rise and fall times are 20 ns.
issi is27lv020 integrated silicon solution, inc. 7 ep019-0a 12/19/97 switching characteristics (1,3,4) (over operating range) jedec std. -90 -12 -15 symbol symbol parameter test conditions min. max. min. max. min. max. unit t avqa t acc address to ce = oe = v il 90 120 150 ns output delay t elqv t ce chip enable to oe = v il 90 120 150 ns output delay c l = c l 1 t glqv t oe output enable to ce = v il 455065ns output delay t ehoz , t df (2) chip enable high or 30 35 35 ns t ghqz output enable high, whichever comes first, to output float t avox t oh output hold from 0 0 0 ns address, ce or oe whichever occured first notes: 1. v cc must be applied simultaneously or before v pp and removed simultaneously or after v pp . 2. this parameter is only sampled, not 100% tested. 3. caution: the is27lv020 must not be removed from (or inserted into) a socket or board when v pp or v cc applied. 4. output load: 1 ttl gate and c l =100 pf. input rise and fall times: 20 ns. input pulse levels: 0.4v to 2.4v. timing measurement reference level: 0.8v to 2v for inputs and outputs. address ce oe output address valid valid output 2.0v 0.8v 2.0v 0.8v t df (2) t oh hi-z hi-z t oe t acc (1) t ce 2.4v 0.4v switching waveforms notes: 1. oe may be delayed up to t acc C t oe after the falling edge of ce without impact on t acc . 2. t df is specified from oe or ce , whichever occurs first.
issi is27lv020 8 integrated silicon solution, inc. ep019-0a 12/19/97 dc programming characteristics (1,2,3,4) (t a = +25 c 5 c) symbol parameter test conditions min. max. unit v oh output high voltage during verify i oh = C400 m a 2.4 v v ol output low voltage during verify i ol = 2.1 ma 0.45 v v ih input high voltage 2.0 v cc + 0.5 v v il input low voltage (all inputs) C0.3 0.8 v v h a9 auto select voltage 11.5 12.5 v i li input current (all inputs) v in = v il or v ih 10.0 m a i cc vcc supply current (program & verify) 50 ma i pp v pp supply current ce = v il , oe = v ih 30ma v cc supply voltage 5.75 6.25 v v pp programming voltage 12.25 12.75 v switch programming characteristics (1,2,3,4) (t a = +25 c 5 c) jedec std. symbol symbol parameter min. max. unit t avel t as address setup time 2 m s t dzgl t oes oe setup time 2 m s t dvel t ds data setup time 2 m s t ghax t ah address hold time 0 m s t ehdx t dh data hold time 2 m s t ghqz t dfp oe high to output float delay 0 130 ns t vps t vps v pp setup time 2 m s t eleh 1 t pw pgm program pulse width 95 105 m s t vcs t vcs v cc setup time 2 m s t elpl t ces ce setup time 2 m s t glqv t oe data valid from oe 150 ns notes: 1. v cc must be applied simultaneously or before v pp and removed simultaneously or after v pp . 2. v pp must be 3 v cc during the entire programming and verifying procedure. 3. when programming is27lv020, a 0.1 m f capacitor is required across v pp and ground to suppress spurious voltage transients which may damage the device. 4. programming characteristics are sampled but not 100% tested at worst-case conditions.
issi is27lv020 integrated silicon solution, inc. 9 ep019-0a 12/19/97 programming algorithm waveform (1,2) program program verify t ah t dfp data out valid hi-z data in stable t as t ds t vps t vcs t ces t pw t dh 12.5v 5.75v-6.25v 3 vcc?.3v 5v 10% t oes t oe max address data v pp v cc ce pgm oe notes: 1. the timing reference level is 0.8v for v il and 2.0v for v ih. 2. t oe and t dfp are characteristics of the device but must be accommodated by the programmer.
issi is27lv020 10 integrated silicon solution, inc. ep019-0a 12/19/97 programming flow chart start address = first location vcc = 6v v pp = 12.5v x = 0 program one 100 s pulse increment x x = 25? yes no last address? pass yes no increment address vcc = v pp = 5.25v fail device failed device passed pass verify byte interactive programming section verify section fail verify all bytes
issi is27lv020 integrated silicon solution, inc. 11 ep019-0a 12/19/97 ordering information commercial rangle: 0 c to +70 c speed (ns) order part number package 90 is27lv020-90w 600-mil plastic dip is27lv020-90pl plcc C plastic leaded chip carrier is27lv020-90t tsop 120 is27lv020-12w 600-mil plastic dip is27lv020-12pl plcc C plastic leaded chip carrier is27lv020-12t tsop 150 is27lv020-15w 600-mil plastic dip IS27LV020-15PL plcc C plastic leaded chip carrier is27lv020-15t tsop ordering information industrial rangle: C40 c to +85 c speed (ns) order part number package 90 is27lv020-90pli plcc C plastic leaded chip carrier is27lv020-90ti tsop 120 is27lv020-12pli plcc C plastic leaded chip carrier is27lv020-12ti tsop 150 IS27LV020-15PLi plcc C plastic leaded chip carrier is27lv020-15ti tsop issi integrated silicon solution, inc. 2231 lawson lane santa clara, ca 95054 fax: (408) 588-0806 toll free: 1-800-379-4774 http://www.issiusa.com

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